As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate exhibiting the requisite reliability. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone, e.g., less than about 15–300 ohm/sq, comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Various metal silicides have been employed in salicide technology, such as titanium, tungsten, and cobalt. Nickel, however, offers particular advantages vis-á-vis other metals in salicide technology. Nickel requires a lower thermal budget in that nickel silicide and can be formed in a single heating step at a relatively low temperature of about 250° C. to about 600° C. with an attendant reduction in consumption of silicon in the substrate, thereby enabling the formation of the ultra-shallow source/drain junctions.
Upon conducting experimentation and investigation to implement nickel silicide formation, it was discovered that the high resistance nickel disilicide phase (NiSi2) is formed on doped silicon and generates an undesirably rough interface therebetween. Such an interface can range in thickness from 200 Å to 1000 Å and can extend but for a short distance, such as 1 micron. Such interface roughness adversely impacts resistivity and capacitance, and can lead to spiking into the source/drain region or through the gate dielectric layer. This problem can become particularly acute in silicon-on-insulator (SOI) structures wherein such spiking can penetrate through to the underlying buried oxide layer and significantly increase contact resistance.
The formation of a rough interface is schematically illustrated in FIG. 1 wherein gate electrode 11 is formed on semiconductor substrate 10 with gate dielectric layer 12 therebetween. Dielectric sidewall spacers 13 are formed on side surfaces of gate electrode 11. Shallow source/drain extensions 14 and moderately or heavily source/drain region 15 are formed. A layer of nickel is deposited followed by heating to effect silicidation resulting in the formation of nickel silicide layers 16 on the source/drain regions and 15 nickel silicide layer 17 on gate electrode 11. The interface 18 between nickel silicide layers 16 and substrate 10 and the interface 19 between the nickel silicide layer and gate electrode 11, is extremely rough and can generate the aforementioned-problems, including spiking intro the substrate 10 as well as penetration through gate dielectric layer 12.
Conventional wisdom is that NiSi2 forms at a temperature of about 600° C., and that the actual formation temperatures are a function of the linewidth and doping type. However, upon conducting further experimentation and investigation, it was found that NiSi2 can form at a very low temperature, even lower that 450° C., such as 310° C. Since nickel diffuses very rapidly, it is extremely difficult to prevent formation of NiSi2 and, hence, rough interfaces.
Additional problems have been encountered in attempting to implement nickel silicidation. In conventional salicide technology, a layer of the metal is deposited on the gate electrode and on the exposed surfaces of the source/drain regions, followed by heating to react the metal with underlying silicon to form the metal silicide. Unreacted metal is then removed from the dielectric sidewall spacers leaving metal silicide contacts on the upper surface of the gate electrode and on the source/drain regions. In implementing salicide technology, it was also found advantageous to employ silicon nitride sidewall spacers, since silicon nitride is highly conformal and enhances device performance, particularly for p-type transistors. However, although silicon nitride spacers are advantageous from such processing standpoints, it was found extremely difficult to effect nickel silicidation of the gate electrode and source/drain regions without undesirable nickel silicide bridging and, hence, short circuiting, therebetween along the surface of the silicon nitride sidewall spacers.
Accordingly, there exists a need for semiconductor devices having nickel silicide interconnections with reduced roughness at the interface between nickel silicide layers and underlying silicon, and for enabling methodology. There also exists a need to implement nickel silicide technology without bridging between the nickel silicide layers on the gate electrode and the source/drain regions, particularly when employing silicon nitride sidewall spacers on the gate electrode.